A high speed DC coupled logic level translator is particularly useful for high speed, high current CMOS drivers. An example of the use of this type of circuit would be in an ultrasound transducer driver high voltage output stage. In this case, an NMOS high voltage transistor with its source grounded would be arranged with its drain connected to the drain of a PMOS high voltage transistor with its source connected to a supply of high voltage. The high voltage could for example be 200 volts DC, whereas the transistors require only 5 to 12 volts of signal between their gate and source terminals for operation. Designate the high voltage supply as VPP, the grounded low voltage supply as VDX, and a floating low voltage supply as VPX. VPX is typically negative relative to VPP, giving a voltage level below VPP for driving the PMOS output transistor, and the other supplies are positive. Low voltage logic circuits could easily provide the gate drive signal for the NMOS transistor, but the PMOS transistor is more difficult to drive since its source is connected to VPP. An auxiliary floating power supply VPX referenced to the high voltage supply can provide power for floating logic circuitry attached to it, but a means must be provided for transmission of the fast logic signals from near ground level to near VPP. The logic swings in both the grounded logic circuitry and the floating logic circuitry would typically be the same, approximately 12 volts in the present example, but this is not a requirement. Therefore both VDX and (VPP-VPX) would be 12 volts for this example.
Problems with the logic signal transfer can be caused by transient or fast changes in the high voltage interfering with the coupling of the logic signals across the voltage barrier. One means which has been successfully used to overcome this problem is to use large pulsed currents in the transfer circuitry. The current pulses are larger than any capacitive displacement currents caused by expected voltage transients, so the circuit operates without error. Power is minimized by use of very short current pulses to transfer information about logic state changes. However, a simpler solution not requiring large pulsed currents in the transfer circuitry would be desirable.
Therefore, a need exists to provide a device and method to overcome the above problem. The device and method will provide a high speed logic signal level shifter. The high speed logic level shifter must be able to transfer a fast logic signal across a high voltage difference between two circuit sections in an integrated circuit. The high speed logic level shifter must be able to transfer a fast logic signal across a high voltage difference between two circuit sections in an integrated circuit without using large pulsed currents in the transfer circuitry.